EP2A40F1020C9N vs EP2A40F1020C8N Vergleich
Detaillierter Direktvergleich von EP2A40F1020C9N von Intel und EP2A40F1020C8N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40F1020C9N | EP2A40F1020C8N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $175,00 | $0,00 |
| Family | APEX II | — |
| Series | EP2A40 | — |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| Logic Family | CMOS | — |
| System Gates | 1.5 M | — |
| Logic Cells / Elements | 38,400 | — |
| Maximum Operating Frequency | 366 MHz | — |
| Propagation Delay | 1.55 ns | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | — |
| User I/O Pins | 735 | — |
| Total Pins | 1020 | — |
| Gehäuse | 1020-ball FC-FBGA, 33 × 33 mm, 1 mm pitch, FineLine | — |
| Betriebstemperatur | 0 °C to 85 °C | 0 °C to 85 °C |
| I/O Standards | True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, GTL+, SSTL | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| On-chip Memory | Embedded System Blocks (ESB) for RAM/ROM | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | unknown | unknown |
| Product Type | — | Field-Programmable Gate Array (FPGA) |
| Device Family | — | APEX II |
| Logic Technology | — | CMOS |
| Logic Gates | — | 1.5 million |
| Logic Cells | — | 38,400 |
| Nominal Supply Voltage | — | 1.5 V |
| Supply Voltage Range | — | 1.425 V to 1.575 V |
| User I/Os | — | 735 |
| Package Terminal Count | — | 1,020 pins |
| Package Type | — | FC-FBGA, BGA-1020 |
| Package Body Size | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Reported Operating Frequency | — | 376 MHz |
| Alternative Reported Frequency | — | 562 MHz |
| Reported Propagation Delay | — | 1.78 ns |
| Alternative Reported Propagation Delay | — | 1.55 ns |
| Fabrication Process | — | 0.15 µm |
| Maximum Reported Metal Layers | — | 8 layers |
| Terminal Form | — | Ball |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |