EP2A40F672C6 vs EP2A40F672C9 Vergleich
Detaillierter Direktvergleich von EP2A40F672C6 von Altera und EP2A40F672C9 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera
EP2A40F672C9 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2A40F672C6 | EP2A40F672C9 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $105,00 | $62,00 |
| Family | APEX II | APEX II |
| Device | EP2A40 | — |
| Logic Elements (typical) | 40,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O count] | — |
| Gehäuse | 672-ball FineLine BGA (FBGA-672) | 672-BBGA, FC-FBGA (FineLine) |
| Speed Grade | C6 (commercial) | — |
| Betriebstemperatur | Commercial (0C to +85C) | 0 °C to 85 °C (commercial) |
| Process Technology | 0.18-micron CMOS | 0.15 µm all-layer copper, up to 8 metal layers |
| Configuration Memory | SRAM-based | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| PLL Support | Yes | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Lifecycle | Obsolete / EOL (per Intel/Altera product discontinuation notice) | — |
| Device Family | — | APEX II PLD |
| Logic Elements / Cells | — | 38,400 |
| System Gates | — | 1.5 M |
| Macros | — | 2,560 |
| User I/Os | — | 492 |
| Anzahl der Pins | — | 672 |
| Package Size | — | 27 mm × 27 mm, 1 mm ball pitch |
| Core Voltage | — | 1.5 V |
| Logic Family | — | CMOS |
| Propagation Delay | — | 1.55 ns |
| Internal Speed Grade | — | 366 MHz |
| I/O Standards Supported | — | True-LVDS, LVPECL, PCML, HyperTransport |