EP2A40F672C6N vs EP2A40F672C7ES Vergleich
Detaillierter Direktvergleich von EP2A40F672C6N von Intel und EP2A40F672C7ES von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2A40F672C6N | EP2A40F672C7ES |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $165,00 | $124,75 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38400 |
| Maximum System Gates | 1,125,000 | — |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Core Voltage | 1.5 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| Gehäuse | 672-ball FineLine BGA | 672-pin FC-FBGA (FineLine BGA) |
| Betriebstemperatur | Commercial (0C to +85C) | 0 °C to +85 °C (commercial) |
| Speed Grade | C6 (per part number suffix) | 7 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 µm CMOS |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Typical Gates | — | 1.5 M |
| Maximum Logic Elements | — | 40960 |
| Maximum Macro Cells | — | 2560 |
| Maximum User I/O | — | 492 |
| Maximum Operating Frequency | — | 562 MHz |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V |
| Package Dimensions | — | 27 × 27 mm |
| Ball Pitch | — | 1.0 mm |
| Status Code | — | ES (Engineering Sample) |