EP2AGX125EF35C6G vs EP2AGX125EF35C4G Vergleich
Detaillierter Direktvergleich von EP2AGX125EF35C6G von Altera und EP2AGX125EF35C4G von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2AGX125EF35C4G - Arria II GX FPGA, 118K LEs, 1152-FCBGA | Intel
EP2AGX125EF35C4G ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2AGX125EF35C6G | EP2AGX125EF35C4G |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Unknown | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $1.290,00 |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Series | Arria II GX | — |
| Number of Logic Elements/Cells | 118143 | — |
| Total RAM Bits | 8315904 bit | — |
| User I/O Pins | 452 | — |
| Core Supply Voltage | 0.87 V to 0.93 V | — |
| Number of LABs | [DATA_NEEDED: number of LABs] | — |
| Betriebstemperatur | 0 °C to 85 °C (Tj) | 0C to +85C (Commercial) |
| Package Type | 1152-BBGA, FCBGA | — |
| Supplier Device Package | 1152-FBGA (35 mm x 35 mm) | — |
| Package Pin Count | 1152 pin | — |
| Montageart | [DATA_NEEDED: mounting type] | Surface Mount |
| Maximum Operating Frequency | [DATA_NEEDED: maximum operating frequency] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | SRAM-based, PS/FPP/JTAG |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Family | — | Arria II GX |
| Logic Elements | — | 118,143 |
| Embedded Memory Bits | — | 8,315,904 |
| Memory Blocks (M9K) | — | [DATA_NEEDED: M9K count] |
| Hardware Multipliers (18x18) | — | 452 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Transceiver Channels | — | 12 |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| PCI Express Hard IP | — | Gen1/Gen2 x1/x4/x8 |
| Core Voltage | — | 0.9 V |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Maximum User I/O | — | [DATA_NEEDED: max user I/O count] |
| Process Technology | — | 40 nm |
| Gehäuse | — | 1152-ball FC-FBGA (Flip-Chip) |
| Speed Grade | — | C4 |
| Lead-Free | — | Yes |