EP2S130F1020I4N vs EP2S130F1020C5N Vergleich
Detaillierter Direktvergleich von EP2S130F1020I4N von Intel und EP2S130F1020C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2S130F1020I4N - Stratix II 132K LEs FPGA, 742 I/O | Intel / Altera
EP2S130F1020I4N ✗ Abgekündigt
Spezifikationsvergleich
| Parameter | EP2S130F1020I4N | EP2S130F1020C5N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Ende des Lebenszyklus | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.380,00 | $1.320,00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Logic Array Blocks (LABs) | 6,627 | — |
| Total RAM Bits | 6,747,840 | — |
| User I/O Count | 742 | — |
| Core Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Betriebstemperatur | -40C to +100C (TJ, Industrial) | Commercial (0C to +85C, C5 grade) |
| Gehäuse / Bauform | 1020-BBGA (FineLine BGA, FC-FBGA) | — |
| Supplier Device Package | 1020-FBGA | — |
| Montageart | Surface Mount | Surface Mount |
| Process Node | 90 nm | — |
| Internal Operating Frequency | up to 711.24 MHz | — |
| Speed Grade | I4 (Industrial, speed bin 4) | — |
| Configuration | SRAM-based, volatile configuration memory | — |
| Design Software | Quartus II (legacy) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free / lead-bearing finish] | [DATA_NEEDED: lead-free status] |
| Adaptive Logic Modules (ALMs) | — | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | — | 6,747,840 bits |
| User I/Os | — | 734 |
| Process Technology | — | 90 nm |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Gehäuse | — | 1020-ball FC-FBGA (33x33 mm) |
| Temperature Grade | — | C5 (other - per Partstack) |
| PLLs | — | 4 (typical Stratix II feature) |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |