EP2S130F1020I4N vs EP2S130F1020C5N Comparison
Detailed side-by-side comparison of EP2S130F1020I4N by Intel and EP2S130F1020C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2S130F1020I4N
EP2S130F1020I4N - Stratix II 132K LEs FPGA, 742 I/O | Intel / Altera
EP2S130F1020I4N β End of LifeIntel
EP2S130F1020C5N
EP2S130F1020C5N - Stratix II FPGA, 132K LEs, 1020-FBGA | Intel
EP2S130F1020C5N NrndSpecification Comparison
| Parameter | EP2S130F1020I4N | EP2S130F1020C5N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Eol | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,380.00 | $1,320.00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Logic Array Blocks (LABs) | 6,627 | β |
| Total RAM Bits | 6,747,840 | β |
| User I/O Count | 742 | β |
| Core Voltage (VCCINT) | 1.15 V to 1.25 V | β |
| Operating Temperature | -40C to +100C (TJ, Industrial) | Commercial (0C to +85C, C5 grade) |
| Package / Case | 1020-BBGA (FineLine BGA, FC-FBGA) | β |
| Supplier Device Package | 1020-FBGA | β |
| Mounting Type | Surface Mount | Surface Mount |
| Process Node | 90 nm | β |
| Internal Operating Frequency | up to 711.24 MHz | β |
| Speed Grade | I4 (Industrial, speed bin 4) | β |
| Configuration | SRAM-based, volatile configuration memory | β |
| Design Software | Quartus II (legacy) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free / lead-bearing finish] | [DATA_NEEDED: lead-free status] |
| Adaptive Logic Modules (ALMs) | β | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | β | 6,747,840 bits |
| User I/Os | β | 734 |
| Process Technology | β | 90 nm |
| Core Supply Voltage (VCCINT) | β | 1.15 V to 1.25 V |
| Maximum Internal Frequency | β | 609.76 MHz |
| Package | β | 1020-ball FC-FBGA (33x33 mm) |
| Temperature Grade | β | C5 (other - per Partstack) |
| PLLs | β | 4 (typical Stratix II feature) |
| Global Clock Networks | β | 16 (typical Stratix II feature) |
| Configuration Method | β | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | β | Republic of Korea (per GlobalSpec) |
| ECCN | β | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | β | 2023 (per GlobalSpec) |