EP2S15F672C4 vs EP2C50F672C8N Vergleich
Detaillierter Direktvergleich von EP2S15F672C4 von Altera und EP2C50F672C8N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2C50F672C8N - Cyclone II FPGA, 50K LE, 672-BGA | Intel / Altera
EP2C50F672C8N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2S15F672C4 | EP2C50F672C8N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $235,00 | $148,75 |
| Family | Stratix II | — |
| Logic Elements | 15,600 | — |
| Embedded Memory Bits | 419,328 bits | — |
| DSP Blocks | 156 (approximate, per Stratix II family) | — |
| Maximum User I/Os | 366 | — |
| Gehäuse | 672-ball FineLine BGA (FBGA) | 672-FBGA (FineLine BGA) |
| Process Node | 90 nm | — |
| PLLs | 6 | — |
| Betriebstemperatur | Commercial (0C to +85C, 'C' suffix) | 0C to +85C (commercial) |
| Speed Grade | 4 | C8 |
| Configuration Method | Serial / Parallel (passive serial, fast passive parallel, JTAG) | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance per Altera product page] | [DATA_NEEDED: rohs status from datasheet] |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | — |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Series | — | Cyclone II |
| Number of Logic Elements | — | 50,528 |
| Number of Logic Array Blocks (LABs) | — | 4,608 |
| Total RAM Bits | — | 594,432 |
| Number of I/O | — | 450 |
| Number of User I/O Banks | — | 8 (per family architecture) |
| Number of PLLs | — | 4 |
| Number of DLLs | — | 2 |
| Embedded 18x18 Multipliers | — | 86 |
| Core Voltage | — | 1.2 V |
| Package Body Size | — | 27 mm x 27 mm |
| Montageart | — | Surface Mount |
| Process Technology | — | 90 nm low-k CMOS |
| Configuration | — | JTAG + serial/parallel |