EP2S15F672C4 vs EP2S15F672C3 Vergleich

Detaillierter Direktvergleich von EP2S15F672C4 von Altera und EP2S15F672C3 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2S15F672C4 EP2S15F672C3
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $235,00 $142,30
Family Stratix II Stratix II
Logic Elements 15,600 15,600
Embedded Memory Bits 419,328 bits —
DSP Blocks 156 (approximate, per Stratix II family) —
Maximum User I/Os 366 —
Gehäuse 672-ball FineLine BGA (FBGA) 672-ball FC-FBGA
Process Node 90 nm —
PLLs 6 [DATA_NEEDED: number of PLLs]
Betriebstemperatur Commercial (0C to +85C, 'C' suffix) —
Speed Grade 4 C3 (third commercial speed bin)
Configuration Method Serial / Parallel (passive serial, fast passive parallel, JTAG) —
I/O Standards Supported LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) —
RoHS-Status [DATA_NEEDED: RoHS compliance per Altera product page] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free finish status] —
MSL-Level [DATA_NEEDED: MSL moisture sensitivity level] [DATA_NEEDED: moisture sensitivity level]
Embedded Memory (bits) — 419,328
DSP Blocks (18-bit multipliers) — 156
Maximum User I/O — 366
Core Voltage — 1.2 V
Process Technology — 90 nm CMOS
Maximum Internal Frequency — [DATA_NEEDED: max internal clock MHz]
Montageart — Surface Mount
Operating Temperature Grade — Commercial (C3 suffix)
Global Clock Networks — [DATA_NEEDED: number of global clocks]

Datenblätter & Ressourcen

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