EP2S15F672C4 vs EP2S15F672C3 对比

详细并排对比 EP2S15F672C4 出自 Altera 和 EP2S15F672C3 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S15F672C4 EP2S15F672C3
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $235.00 $142.30
Family Stratix II Stratix II
Logic Elements 15,600 15,600
Embedded Memory Bits 419,328 bits —
DSP Blocks 156 (approximate, per Stratix II family) —
Maximum User I/Os 366 —
封装 672-ball FineLine BGA (FBGA) 672-ball FC-FBGA
Process Node 90 nm —
PLLs 6 [DATA_NEEDED: number of PLLs]
工作温度 Commercial (0C to +85C, 'C' suffix) —
Speed Grade 4 C3 (third commercial speed bin)
Configuration Method Serial / Parallel (passive serial, fast passive parallel, JTAG) —
I/O Standards Supported LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) —
RoHS 状态 [DATA_NEEDED: RoHS compliance per Altera product page] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free finish status] —
MSL 等级 [DATA_NEEDED: MSL moisture sensitivity level] [DATA_NEEDED: moisture sensitivity level]
Embedded Memory (bits) — 419,328
DSP Blocks (18-bit multipliers) — 156
Maximum User I/O — 366
Core Voltage — 1.2 V
Process Technology — 90 nm CMOS
Maximum Internal Frequency — [DATA_NEEDED: max internal clock MHz]
安装类型 — Surface Mount
Operating Temperature Grade — Commercial (C3 suffix)
Global Clock Networks — [DATA_NEEDED: number of global clocks]

数据手册与资源

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