EP2S30F672C4 vs EP2S30F672I4 Vergleich
Detaillierter Direktvergleich von EP2S30F672C4 von Intel und EP2S30F672I4 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2S30F672C4 | EP2S30F672I4 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $498,43 | $695,00 |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Series | Stratix II | Stratix II |
| Logic Elements / Cells | 33,880 | — |
| Total RAM Bits | 1,369,728 | 1369728 |
| Number of I/O | 500 | 500 |
| Gehäuse | 672-BBGA, FCBGA (27x27 mm) | — |
| Montageart | Surface Mount | Surface Mount |
| Core Voltage - Supply | 1.15 V to 1.25 V | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Maximum Core Frequency (datasheet benchmark) | 711 MHz | — |
| Betriebstemperatur | 0C to +85C (commercial, 'C' speed grade) | -40C to +100C (Industrial) |
| Embedded DSP Blocks | 16 (Stratix II S30 tier) | — |
| Number of PLLs | [DATA_NEEDED: PLL count for S30 tier] | 6 |
| Number of Global Clock Networks | [DATA_NEEDED: global clock network count] | — |
| RoHS-Status | Compliant | [DATA_NEEDED: confirm RoHS compliance on part label] |
| Lead-Free | Yes | — |
| Logic Elements | — | 33880 |
| Logic Array Blocks (LABs) | — | 1694 |
| DSP Blocks | — | 12 (per datasheet, family range) |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| Gehäuse / Bauform | — | 672-BBGA, FCBGA (FBGA-672) |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |
| Configuration | — | JTAG, serial, parallel (Stratix II scheme) |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |