EP2S30F672C4 vs EP2S30F672I4 对比
详细并排对比 EP2S30F672C4 出自 Intel 和 EP2S30F672I4 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2S30F672C4 | EP2S30F672I4 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $498.43 | $695.00 |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Series | Stratix II | Stratix II |
| Logic Elements / Cells | 33,880 | — |
| Total RAM Bits | 1,369,728 | 1369728 |
| Number of I/O | 500 | 500 |
| 封装 | 672-BBGA, FCBGA (27x27 mm) | — |
| 安装类型 | Surface Mount | Surface Mount |
| Core Voltage - Supply | 1.15 V to 1.25 V | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Maximum Core Frequency (datasheet benchmark) | 711 MHz | — |
| 工作温度 | 0C to +85C (commercial, 'C' speed grade) | -40C to +100C (Industrial) |
| Embedded DSP Blocks | 16 (Stratix II S30 tier) | — |
| Number of PLLs | [DATA_NEEDED: PLL count for S30 tier] | 6 |
| Number of Global Clock Networks | [DATA_NEEDED: global clock network count] | — |
| RoHS 状态 | Compliant | [DATA_NEEDED: confirm RoHS compliance on part label] |
| Lead-Free | Yes | — |
| Logic Elements | — | 33880 |
| Logic Array Blocks (LABs) | — | 1694 |
| DSP Blocks | — | 12 (per datasheet, family range) |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| 封装 / 外壳 | — | 672-BBGA, FCBGA (FBGA-672) |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |
| Configuration | — | JTAG, serial, parallel (Stratix II scheme) |
| MSL 等级 | — | 3 (per JEDEC J-STD-020) |