EP2S30F672I4 vs EP2S30F672C5N Vergleich
Detaillierter Direktvergleich von EP2S30F672I4 von Intel und EP2S30F672C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2S30F672I4 | EP2S30F672C5N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $695,00 | $450,00 |
| Series | Stratix II | Stratix II |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 33880 | 33,880 |
| Logic Array Blocks (LABs) | 1694 | 1694 |
| Total RAM Bits | 1369728 | — |
| Number of I/O | 500 | — |
| DSP Blocks | 12 (per datasheet, family range) | [DATA_NEEDED: DSP block count] |
| Number of PLLs | 6 | 4 |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | — |
| Betriebstemperatur | -40C to +100C (Industrial) | — |
| Montageart | Surface Mount | — |
| Gehäuse / Bauform | 672-BBGA, FCBGA (FBGA-672) | — |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | — |
| MSL-Level | 3 (per JEDEC J-STD-020) | — |
| RoHS-Status | [DATA_NEEDED: confirm RoHS compliance on part label] | — |
| Family Name | — | Stratix II |
| Embedded Memory (bits) | — | 1,369,728 |
| User I/O Count | — | 500 |
| Gehäuse | — | 672-ball FBGA (FineLine BGA) |
| Speed Grade | — | C5 (-5 commercial) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core VCC value] |
| Betriebstemperaturbereich | — | Commercial (0C to +85C) |
| Global Clock Networks | — | 16 |
| Configuration Method | — | Serial / Passive Parallel / Fast Passive Parallel |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Architecture | — | Adaptive Logic Module (ALM) |
| Multipliers | — | [DATA_NEEDED: 18x18 multiplier count] |