EP2S30F672I4N vs EP2S60F67214N Vergleich
Detaillierter Direktvergleich von EP2S30F672I4N von Altera und EP2S60F67214N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP2S30F672I4N | EP2S60F67214N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $145,00 | $232,00 |
| Family | Stratix II | Stratix II |
| Logic Elements (LEs) | 33,880 | — |
| Logic Array Blocks (LABs) | 1,694 | — |
| Total RAM Bits | 1,369,728 | 2,544,192 bit (2.5 Mbit) |
| Maximum User I/Os | 500 | — |
| Gehäuse | 672-BBGA, FCBGA (27x27 mm) | 672-ball FBGA (FineLine BGA) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40C to +100C (industrial) | -40C to +100C (industrial) |
| Core Supply Voltage | 1.15 V to 1.25 V | — |
| Technology Node | 90 nm | — |
| Speed Grade | I4 (speed grade 4, industrial) | I4 (industrial, fast) |
| Versorgungsspannung | 1.15 V to 1.25 V | — |
| Maximum Frequency | 711.24 MHz | — |
| MSL-Level | 3 (per JEDEC J-STD-020) | 3 (168 hours floor life) |
| RoHS-Status | Compliant | Lead-free / RoHS compliant |
| Logic Elements | — | 60,440 LE |
| DSP Blocks | — | 12 |
| Phase-Locked Loops (PLLs) | — | 4 |
| Process Technology | — | 90 nm CMOS |
| Core Voltage | — | 1.2 V (typical) |
| I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count for FBGA-672] |
| Configuration | — | SRAM-based, configured via bitstream |