EP2S90F1020C4N vs EP2S90F1020C3N Vergleich
Detaillierter Direktvergleich von EP2S90F1020C4N von Intel und EP2S90F1020C3N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP2S90F1020C3N - 90nm Stratix II FPGA 90,960 LEs FC-FBGA-1020 | Altera
EP2S90F1020C3N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2S90F1020C4N | EP2S90F1020C3N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.320,00 | $1.995,00 |
| Family | Stratix II | Stratix II (EP2S90) |
| Logic Elements (LEs) | 90,960 | — |
| LABs/CLBs | 4,548 | — |
| Total Memory Bits | 4,520,488 | — |
| User I/Os | 758 | — |
| Anzahl der Pins | 1020 | — |
| Package Type | FC-FBGA (Flip-Chip Fine-pitch BGA) | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | — |
| Maximum Fabric Frequency | 711.24 MHz | — |
| Operating Temperature Grade | Commercial (C4 suffix) | — |
| Montageart | Surface Mount | Surface Mount |
| Configuration Method | JTAG / Passive Serial / Passive Parallel / Active Serial | — |
| RoHS-Status | Compliant | Compliant |
| Lebenszyklusstatus | Not Recommended for New Designs (NRND) | — |
| Series | — | Stratix II |
| Logic Elements | — | 90,960 |
| LABs (Logic Array Blocks) | — | 4,548 |
| Total RAM Bits | — | 4,520,488 |
| User I/O Count | — | 758 |
| Supply Voltage - Core | — | 1.15 V to 1.25 V (1.2 V nominal) |
| Betriebstemperatur | — | 0C to +85C (commercial grade) |
| Speed Grade | — | C3 (commercial, slowest) |
| Gehäuse / Bauform | — | 1020-BBGA, FC-FBGA |
| Supplier Device Package | — | 1020-FBGA (33 x 33 mm) |
| DSP Block Count | — | [DATA_NEEDED: 18x18 multiplier count] |
| Embedded Transceivers | — | [DATA_NEEDED: number of high-speed transceivers] |
| Maximum User I/O Frequency | — | [DATA_NEEDED: LVDS / DDR max rate] |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |
| Programming Tool | — | Altera Quartus II |