EP2S90F1020C4N vs EP2S90F1020C3N Comparación
Comparación detallada lado a lado de EP2S90F1020C4N por Intel y EP2S90F1020C3N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP2S90F1020C3N - 90nm Stratix II FPGA 90,960 LEs FC-FBGA-1020 | Altera
EP2S90F1020C3N ⚠ Última compraComparación de especificaciones
| Parámetro | EP2S90F1020C4N | EP2S90F1020C3N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.320,00 | $1.995,00 |
| Family | Stratix II | Stratix II (EP2S90) |
| Logic Elements (LEs) | 90,960 | — |
| LABs/CLBs | 4,548 | — |
| Total Memory Bits | 4,520,488 | — |
| User I/Os | 758 | — |
| Número de pines | 1020 | — |
| Package Type | FC-FBGA (Flip-Chip Fine-pitch BGA) | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | — |
| Maximum Fabric Frequency | 711.24 MHz | — |
| Operating Temperature Grade | Commercial (C4 suffix) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Method | JTAG / Passive Serial / Passive Parallel / Active Serial | — |
| Estado RoHS | Compliant | Compliant |
| Estado del ciclo de vida | Not Recommended for New Designs (NRND) | — |
| Series | — | Stratix II |
| Logic Elements | — | 90,960 |
| LABs (Logic Array Blocks) | — | 4,548 |
| Total RAM Bits | — | 4,520,488 |
| User I/O Count | — | 758 |
| Supply Voltage - Core | — | 1.15 V to 1.25 V (1.2 V nominal) |
| Temperatura de funcionamiento | — | 0C to +85C (commercial grade) |
| Speed Grade | — | C3 (commercial, slowest) |
| Encapsulado / Carcasa | — | 1020-BBGA, FC-FBGA |
| Supplier Device Package | — | 1020-FBGA (33 x 33 mm) |
| DSP Block Count | — | [DATA_NEEDED: 18x18 multiplier count] |
| Embedded Transceivers | — | [DATA_NEEDED: number of high-speed transceivers] |
| Maximum User I/O Frequency | — | [DATA_NEEDED: LVDS / DDR max rate] |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |
| Programming Tool | — | Altera Quartus II |