EP3CLS100U484I7N vs EP3CLS100U484C7N Vergleich
Detaillierter Direktvergleich von EP3CLS100U484I7N von Altera und EP3CLS100U484C7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3CLS100U484I7N | EP3CLS100U484C7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $108,00 | $412,65 |
| Device Family | Cyclone III LS | Cyclone III LS |
| Series | Cyclone III | — |
| Logic Elements (LE) | 100,448 | — |
| Total RAM Bits | 4,451,328 bits (~4.4 Mbit) | — |
| Maximum User I/O | 278 | — |
| Number of LABs | 6,278 | — |
| DSP Blocks | 24 (18x18 multipliers) | — |
| Embedded Memory | 432 M9K blocks (9 Kbit each) | 4,451,328 bits (4.4 Mbit) |
| PLLs | 4 | [DATA_NEEDED: PLL count] |
| Core Supply Voltage | 1.2 V | 1.2 V |
| I/O Supply Voltage | 1.2 V to 3.3 V (per bank) | — |
| Gehäuse | 484-FBGA (UBGA) | 484-ball FBGA (UBGA) |
| Betriebstemperatur | -40C to +100C (Industrial, 'I') | 0C to +85C (commercial) |
| Process Technology | TSMC 65 nm low-power (LP) | 65 nm TSMC low-power |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Security Features | AES-128 bit-stream encryption, JTAG disable, tamper detection | — |
| RoHS-Status | Compliant | Compliant |
| MSL-Level | 3 (168 hours) | — |
| Logic Elements | — | 100,448 |
| User I/O Pins | — | 278 |
| Speed Grade | — | 7 (commercial) |
| Maximum Internal Frequency | — | 437.5 MHz |
| Configuration Mode | — | AS / AP / PS / JTAG |
| DSP Blocks (18x18 multipliers) | — | [DATA_NEEDED: DSP block count] |
| I/O Banks | — | 8 |
| Lead-Free | — | Yes |