EP3CLS100U484I7N vs EP3CLS100U484C7N 比較
詳細な並列比較: EP3CLS100U484I7N メーカー: Altera および EP3CLS100U484C7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP3CLS100U484I7N | EP3CLS100U484C7N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $108.00 | $412.65 |
| Device Family | Cyclone III LS | Cyclone III LS |
| Series | Cyclone III | — |
| Logic Elements (LE) | 100,448 | — |
| Total RAM Bits | 4,451,328 bits (~4.4 Mbit) | — |
| Maximum User I/O | 278 | — |
| Number of LABs | 6,278 | — |
| DSP Blocks | 24 (18x18 multipliers) | — |
| Embedded Memory | 432 M9K blocks (9 Kbit each) | 4,451,328 bits (4.4 Mbit) |
| PLLs | 4 | [DATA_NEEDED: PLL count] |
| Core Supply Voltage | 1.2 V | 1.2 V |
| I/O Supply Voltage | 1.2 V to 3.3 V (per bank) | — |
| パッケージ | 484-FBGA (UBGA) | 484-ball FBGA (UBGA) |
| 動作温度 | -40C to +100C (Industrial, 'I') | 0C to +85C (commercial) |
| Process Technology | TSMC 65 nm low-power (LP) | 65 nm TSMC low-power |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| Security Features | AES-128 bit-stream encryption, JTAG disable, tamper detection | — |
| RoHS ステータス | Compliant | Compliant |
| MSLレベル | 3 (168 hours) | — |
| Logic Elements | — | 100,448 |
| User I/O Pins | — | 278 |
| Speed Grade | — | 7 (commercial) |
| Maximum Internal Frequency | — | 437.5 MHz |
| Configuration Mode | — | AS / AP / PS / JTAG |
| DSP Blocks (18x18 multipliers) | — | [DATA_NEEDED: DSP block count] |
| I/O Banks | — | 8 |
| Lead-Free | — | Yes |