EP3SE260F1517C4L vs EP3SE260H780C4LG Vergleich
Detaillierter Direktvergleich von EP3SE260F1517C4L von Altera und EP3SE260H780C4LG von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3SE260F1517C4L | EP3SE260H780C4LG |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15.100,00 | $1.290,00 |
| Family | Stratix III E | Stratix III Enhanced (EP3SE) |
| Logic Elements | 255,000 | 254,400 |
| Embedded Memory Bits | 16,672,768 | — |
| Number of User I/O | 976 | — |
| Gehäuse | 1517-BBGA, FCBGA (FineLine BGA) | 780-ball FineLine BGA (HBGA, 29 mm x 29 mm, 1.0 mm pitch) |
| Process Technology | 65 nm | 65 nm TSMC low-power CMOS |
| Core Voltage | 1.1 V | — |
| Maximum Operating Frequency | 450 MHz | — |
| Number of Transceivers | 16 | — |
| Transceiver Data Rate (Max) | 1.25 Gbps | — |
| Multiplier Blocks (18x18) | 384 | — |
| Total TriMatrix Memory | 15.04 Mbits (MLAB + M9K + M144K) | — |
| PLLs | 4 per quadrant + 8 fractional PLLs | — |
| Betriebstemperatur | 0C to +85C (commercial) | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant (Pb-free HBGA) |
| Adaptive Logic Modules (ALMs) | — | 101,760 |
| Embedded Memory (M9K + M144K) | — | 18.36 Mbits |
| DSP Blocks (18-bit x 18-bit) | — | 768 |
| 18-bit x 18-bit Multipliers | — | 1,536 |
| Transceivers (full-duplex) | — | 8 (up to 6.375 Gbps) |
| Maximum User I/O Pins | — | 488 |
| Speed Grade | — | C4 (commercial, mid-speed tier) |
| Temperature Grade | — | Commercial (0C to +85C junction) |
| Operating Voltage (Core) | — | 0.9 V / 1.0 V / 1.1 V (programmable) |
| External Memory Interface | — | Up to 800 Mbps DDR3, QDR II+, RLDRAM II |
| Hard IP Blocks | — | PCIe Gen2, 10GbE MAC, memory controllers |
| MSL-Level | — | 3 (per JEDEC J-STD-020) |