EP3SL200H780I4LN vs EP3SL200H780C3N Vergleich
Detaillierter Direktvergleich von EP3SL200H780I4LN von Altera und EP3SL200H780C3N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3SL200H780I4LN | EP3SL200H780C3N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1.280,00 | $4.995,00 |
| Series | Stratix III L | — |
| Family | Stratix III L (Low-Power) | Stratix III L (low-power) |
| Manufacturer | Intel / Altera (now Intel PSG) | — |
| Number of Logic Elements / Cells | 200,000 | — |
| Number of LABs / CLBs | 8,000 | — |
| Total RAM Bits | 10,901,504 (approximately 10.9 Mbit) | — |
| Number of I/O | 488 | — |
| Voltage - Supply | 0.9 V core (selectable Vcore) | — |
| Betriebstemperatur | -40C to +100C (industrial) | 0C to +85C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| Gehäuse / Bauform | 780-BBGA, FCBGA (Flip-Chip BGA) | — |
| Process Technology | 65 nm CMOS | — |
| Speed Grade | I4 (Industrial, mid-speed grade) | C3 (commercial, -3 speed) |
| RoHS-Status | RoHS Compliant (lead-free) | — |
| MSL-Level | MSL 3 (168 Hours, per JEDEC J-STD-020) | 3 |
| Roaming Pin Name Suffix | LN = lead-free, industrial temp, H780 780-ball package | — |
| Process Node | — | 40 nm |
| Logic Elements | — | 200,000 |
| Embedded Memory Bits | — | 10,901,504 bits |
| Logic Array Blocks (LABs) | — | 8,000 |
| User I/Os | — | 488 |
| Gehäuse | — | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| Maximum Internal Clock Frequency | — | 800 MHz |
| Transceivers | — | 24 channels, up to 3.75 Gbps |
| DSP Blocks | — | 384 |
| Voltage - Core | — | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | — | 1.2 V to 3.3 V (VCCIO banks) |
| Lead-Free / RoHS | — | Yes |
| Mounting Pitch | — | 1.0 mm ball pitch |
| PLLs | — | 12 (Stratix III PLL array) |
| Configuration | — | JTAG IEEE Std 1149.1, passive/active serial |