EP3SL340H1152C2N vs EP3SL340H1152C4L Vergleich
Detaillierter Direktvergleich von EP3SL340H1152C2N von Intel und EP3SL340H1152C4L von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP3SL340H1152C2N - Stratix III L FPGA, 337.5K LE, 1152-BGA | Intel
EP3SL340H1152C2N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP3SL340H1152C2N | EP3SL340H1152C4L |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3.400,00 | $3.500,00 |
| Family | Stratix III L | — |
| Logic Elements | 337,500 | 337,500 |
| Embedded Memory Bits | 18,822,144 | 18,822,144 |
| DSP Blocks (18x18 multipliers) | 744 | — |
| Process Technology | 65 nm CMOS | 65 nm |
| Core Voltage | 0.9 V | — |
| Auxiliary / I/O Supply | 1.1 V | — |
| Maximum Fabric Frequency | 600 MHz | — |
| Gehäuse | 1152-Ball FC-HFBGA (flip-chip) | 1152-BBGA, FCBGA (HBGA) |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Lead-Free / RoHS | Lead-free (per distributor listing) | — |
| Operating Temperature Grade | Commercial | — |
| Speed Grade | C2 (moderate) | C4L (L-suffix low power) |
| JTAG Support | IEEE Std 1149.1 Boundary-Scan | — |
| Speichertyp | TriMatrix (MLAB + M9K + M144K) | — |
| Series | — | Stratix III L |
| Maximum User I/O | — | 744 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded 18x18 Multipliers | — | 384 (per family datasheet) |
| Core Voltage (VCCINT) | — | 1.1 V |
| Betriebstemperatur | — | 0 C to +85 C (commercial) |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Memory | — | SRAM-based, volatile (needs external config device) |
| Maximum Operating Frequency | — | [DATA_NEEDED: per design, ~450 MHz logic per GlobalSpec listing] |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (per family) |