EP3SL50F484C2N vs EP3SE50F484C2G Vergleich
Detaillierter Direktvergleich von EP3SL50F484C2N von Altera und EP3SE50F484C2G von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP3SL50F484C2N - Stratix III L FPGA, 47.5K LE, 484-FBGA | Altera
EP3SL50F484C2N ⚠ Letzte BestellmöglichkeitIntel
EP3SE50F484C2G - Stratix III E FPGA 47.5K LE 484-FBGA | Intel
EP3SE50F484C2G ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP3SL50F484C2N | EP3SE50F484C2G |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $175,00 | $1.180,00 |
| Series | Stratix III L | Stratix III E |
| Family | Stratix III | — |
| Logic Elements | 47,500 | — |
| Logic Array Blocks (LABs) | 1,900 | — |
| Embedded Memory | 2,184,192 bits | — |
| User I/Os | 296 | — |
| Operating Frequency | 600 MHz | — |
| Process Technology | 65 nm | 40 nm TSMC low-power CMOS |
| Core Supply Voltage | 1.1 V | — |
| Gehäuse | 484-ball FC-FBGA (Flip-Chip) | — |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Montageart | Surface Mount | Surface Mount |
| Temperature Grade | Industrial (C2) | — |
| Lead-Free / RoHS | Yes (compliant) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Configuration Method | JTAG / Passive Serial / FPP | — |
| Number of Logic Elements / Cells | — | 47,500 |
| Number of LABs / CLBs | — | 1,900 |
| Total RAM Bits | — | 5,760,000 (5,760 Kbit) |
| Number of User I/O | — | 296 |
| Gehäuse / Bauform | — | 484-BBGA, FCBGA (FineLine BGA) |
| Core Voltage Supply | — | 0.86 V to 1.15 V |
| Betriebstemperatur | — | 0 °C to +85 °C (TJ) |
| Logic Element Architecture | — | Adaptive Logic Module (ALM) with 8-input fracturable LUT |
| Embedded DSP Blocks | — | Yes (variable-precision multipliers) |
| Transceivers | — | Multi-gigabit transceivers (selected package pins) |
| Memory Interface Support | — | DDR / DDR2 / DDR3 with hard PHY |
| Partial Reconfiguration | — | Supported |
| Configuration Interface | — | JTAG, Passive Serial, Fast Passive Parallel |
| Part Status | — | Active (Intel catalogue); long-term supply subject to Stratix III lifecycle policy |
| RoHS-Status | — | Compliant |