EP610DC-30 vs EP610DC-10 Vergleich
Detaillierter Direktvergleich von EP610DC-30 von Altera und EP610DC-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DC-30 | EP610DC-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,40 | $7,95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | — |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Gehäuse | 24-pin CERDIP (windowed) | 24-pin CDIP (Ceramic DIP, windowed) |
| Montageart | Through-Hole | Through-Hole |
| Speed Grade | -30 (30 ns tPD) | -10 |
| Technology | CMOS EPROM | CMOS, EPROM-based (UV-erasable) |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Betriebstemperatur | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Versorgungsspannung | — | 5 V (single supply) |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |
| RoHS-Status | — | [DATA_NEEDED: not stated in verified web data] |