EP610DC-30 vs EP610DC-10 比較
詳細な並列比較: EP610DC-30 メーカー: Altera および EP610DC-10 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610DC-30 | EP610DC-10 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $7.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | — |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| パッケージ | 24-pin CERDIP (windowed) | 24-pin CDIP (Ceramic DIP, windowed) |
| 実装タイプ | Through-Hole | Through-Hole |
| Speed Grade | -30 (30 ns tPD) | -10 |
| Technology | CMOS EPROM | CMOS, EPROM-based (UV-erasable) |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| 動作温度 | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| 電源電圧 | — | 5 V (single supply) |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |
| RoHS ステータス | — | [DATA_NEEDED: not stated in verified web data] |