EP610IDC-15 vs EP610DI-30N Vergleich
Detaillierter Direktvergleich von EP610IDC-15 von Intel und EP610DI-30N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel
EP610IDC-15 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EP610IDC-15 | EP610DI-30N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $17,80 |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 15 ns | 30 ns |
| Maximum Frequency | 66 MHz | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±5% |
| Betriebstemperatur | 0C to +70C (commercial) | -40°C to +85°C (industrial) |
| Process Technology | CMOS, UV-erasable / OTP | CMOS |
| Gehäuse | 24-pin CerDIP (ceramic DIP) | CDIP-24 (Ceramic DIP, windowed) |
| Montageart | Through-hole | Through-hole (DIP) |
| I/O Pins | 24 (per package; macrocell-programmable) | — |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS-Status | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EP610 |
| Pin-Anzahl | — | 24 |
| Programming Method | — | UV-erasable (windowed ceramic) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |