EP610IDC-15 vs EP610DI-30N Comparison
Detailed side-by-side comparison of EP610IDC-15 by Intel and EP610DI-30N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-15 | EP610DI-30N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 15 ns | 30 ns |
| Maximum Frequency | 66 MHz | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±5% |
| Operating Temperature | 0C to +70C (commercial) | -40°C to +85°C (industrial) |
| Process Technology | CMOS, UV-erasable / OTP | CMOS |
| Package | 24-pin CerDIP (ceramic DIP) | CDIP-24 (Ceramic DIP, windowed) |
| Mounting Type | Through-hole | Through-hole (DIP) |
| I/O Pins | 24 (per package; macrocell-programmable) | — |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS Status | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EP610 |
| Pin Count | — | 24 |
| Programming Method | — | UV-erasable (windowed ceramic) |
| MSL Level | — | [DATA_NEEDED: MSL level] |