EP610ILC-10 vs EP610LC-25 Vergleich
Detaillierter Direktvergleich von EP610ILC-10 von Altera und EP610LC-25 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610ILC-10 | EP610LC-25 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,20 | $6,20 |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count] |
| Dedicated Inputs | 4 | — |
| Versorgungsspannung | 5 V (single supply) | 5 V ±5% |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Gehäuse | PLCC-28 (plastic J-lead chip carrier) | PLCC-28 |
| Montageart | Surface Mount (PLCC socket or solder) | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED] |
| Family | — | Classic EPLD |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | 100 MHz |
| Pipelined Data Rate | — | Up to 100 MHz |
| Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |