EP610JI-30 vs EP610ILC-25 Vergleich
Detaillierter Direktvergleich von EP610JI-30 von Altera und EP610ILC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610JI-30 | EP610ILC-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,40 | $9,85 |
| Family | Altera Classic EPLD (EP610) | Classic EPLD (EP610 series) |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | EEPLD (Electrically Erasable PLD) |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Product Terms | 160 | 160 |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| Versorgungsspannung | 5 V (single supply) | — |
| Process Technology | CMOS | CMOS, electrically erasable |
| Gehäuse | CQCC28 (windowed ceramic JLCC, J-bend) | 28-pin PLCC (J-lead) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| Betriebstemperatur | -40C to +85C (industrial, per EP610 family suffix convention) | — |
| Montageart | Surface Mount (JLCC) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Usable Gates | — | 300 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Betriebstemperaturbereich | — | 0 C to +70 C (commercial) |
| Programming Method | — | In-system, electrically erasable |