EP610LC-15 vs EP610LC-30 Vergleich
Detaillierter Direktvergleich von EP610LC-15 von Altera und EP610LC-30 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LC-15 | EP610LC-30 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,65 | $16,40 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP610) | Classic EPLD (EP610) |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | — |
| Propagation Delay (tpd) | 15 ns | — |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Gehäuse | 28-pin PLCC (J-lead, plastic OTP) | 24-pin CERDIP / PDIP |
| Montageart | Surface Mount | Through-Hole |
| Anzahl der Pins | 28 | — |
| Betriebstemperatur | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Programming | OTP (one-time programmable) | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Technology | — | CMOS EPROM (UV-erasable) |
| Erase/Program Cycles | — | 1000 typical |
| Ausgangstyp | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |