EP610LC-30 vs EP610DC-35 Vergleich
Detaillierter Direktvergleich von EP610LC-30 von Intel und EP610DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LC-30 | EP610DC-35 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $18,40 |
| Family | Classic EPLD (EP610) | Altera Classic EP610 |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Gehäuse | 24-pin CERDIP / PDIP | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Betriebstemperatur | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Erase/Program Cycles | 1000 typical | — |
| Montageart | Through-Hole | Through-Hole (DIP) |
| Ausgangstyp | CMOS tri-state (programmable) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |