EP610LC-30 vs EP610DC-35 对比
详细并排对比 EP610LC-30 出自 Intel 和 EP610DC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610LC-30 | EP610DC-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.40 | $18.40 |
| Family | Classic EPLD (EP610) | Altera Classic EP610 |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| 封装 | 24-pin CERDIP / PDIP | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 工作温度 | 0 C to +70 C (commercial) / -55 C to +125 C (military) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Erase/Program Cycles | 1000 typical | — |
| 安装类型 | Through-Hole | Through-Hole (DIP) |
| 输出类型 | CMOS tri-state (programmable) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |