EP610PC-30 vs EP610DC-30 Vergleich

Detaillierter Direktvergleich von EP610PC-30 von Altera und EP610DC-30 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP610PC-30 EP610DC-30
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $27,74 $10,40
Device Family Classic EPLD (EP610) —
Macrocells 16 16
Usable Gates 300 300
Propagation Delay (tPD) 30 ns 30 ns
Maximum Pipeline Frequency 33.3 MHz (typical) / 100 MHz pipelined —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Process Technology CMOS EPROM —
Gehäuse 24-pin PDIP (0.300 inch) 24-pin CERDIP (windowed)
Montageart Through-Hole Through-Hole
Programmability One-Time Programmable (OTP, no window on plastic PDIP) UV-erasable, windowed EPROM
Betriebstemperatur 0C to +70C (commercial) Commercial (0C to +70C)
Output Drive Current [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] —
Input Pins (Dedicated) [DATA_NEEDED: dedicated input count from datasheet pinout] —
I/O Pins [DATA_NEEDED: bidirectional I/O count from datasheet pinout] 16 (with output enable)
Programming Tool Altera A+PLUS / MAX+PLUS II (legacy) —
RoHS-Status Not applicable (legacy non-compliant package per distributor listing) —
Lead Free Status Not applicable —
Current Distributor Rochester Electronics, LLC (authorized continuing source) —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — EP610 (Classic Device Family)
Logic Expanders — 4 (4 product terms per macrocell)
Maximum Pipelined Clock Frequency — 100 MHz
Dedicated Inputs — 16
Speed Grade — -30 (30 ns tPD)
Technology — CMOS EPROM
Security Bit — Yes (protects design after programming)
Output Modes — Registered and Combinatorial

Datenblätter & Ressourcen

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