EP610PC-30 vs EP610DC-30 比較
詳細な並列比較: EP610PC-30 メーカー: Altera および EP610DC-30 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610PC-30 | EP610DC-30 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.74 | $10.40 |
| Device Family | Classic EPLD (EP610) | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 30 ns |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Process Technology | CMOS EPROM | — |
| パッケージ | 24-pin PDIP (0.300 inch) | 24-pin CERDIP (windowed) |
| 実装タイプ | Through-Hole | Through-Hole |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | UV-erasable, windowed EPROM |
| 動作温度 | 0C to +70C (commercial) | Commercial (0C to +70C) |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | — |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | — |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | 16 (with output enable) |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | — |
| RoHS ステータス | Not applicable (legacy non-compliant package per distributor listing) | — |
| Lead Free Status | Not applicable | — |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP610 (Classic Device Family) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |