EP610PC-30 vs EP610PC-25 Vergleich

Detaillierter Direktvergleich von EP610PC-30 von Altera und EP610PC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP610PC-30 EP610PC-25
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $27,74 $9,75
Device Family Classic EPLD (EP610) Classic EPLD (EP610 series)
Macrocells 16 —
Usable Gates 300 300
Propagation Delay (tPD) 30 ns —
Maximum Pipeline Frequency 33.3 MHz (typical) / 100 MHz pipelined —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Process Technology CMOS EPROM —
Gehäuse 24-pin PDIP (0.300 inch) PDIP-24 (0.3 inch, through-hole)
Montageart Through-Hole Through-Hole (DIP)
Programmability One-Time Programmable (OTP, no window on plastic PDIP) —
Betriebstemperatur 0C to +70C (commercial) [DATA_NEEDED: operating temperature grade]
Output Drive Current [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] —
Input Pins (Dedicated) [DATA_NEEDED: dedicated input count from datasheet pinout] —
I/O Pins [DATA_NEEDED: bidirectional I/O count from datasheet pinout] 20 (bidirectional, JTAG-programmable OE per macrocell)
Programming Tool Altera A+PLUS / MAX+PLUS II (legacy) —
RoHS-Status Not applicable (legacy non-compliant package per distributor listing) [DATA_NEEDED: RoHS status]
Lead Free Status Not applicable —
Current Distributor Rochester Electronics, LLC (authorized continuing source) —
Macro Cells — 16
Propagation Delay (tpd) — 25 ns
Maximum Pipelined Data Rate — 100 MHz
Supply Voltage (Vcc) — 5 V (nominal)
Technology — CMOS, EPROM (UV-erasable)
Device Type — OT PLD, PAL-type, CMOS
Dedicated Inputs — 4
Programming Method — EPROM (UV-erasable), via Altera programming hardware

Datenblätter & Ressourcen

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