EP910DC-15 vs EP910IDI-15 Vergleich

Detaillierter Direktvergleich von EP910DC-15 von Altera und EP910IDI-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DC-15 EP910IDI-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $10,75 $29,00
Family Altera Classic EPLD Classic EPLD
Device Density 900 usable gates —
Macrocells 24 24
Logic Elements [DATA_NEEDED: exact LE count] —
Dedicated Inputs 12 —
Bidirectional I/O Pins 12 —
Flip-Flops 10 —
Product Terms per Macrocells 24 —
Maximum Propagation Delay (tPD) 15 ns —
Speed Grade 15 —
Supply Voltage (VCC) 5 V (typical) —
Betriebstemperatur 0C to +70C (commercial) -40C to +85C (industrial, "I" grade)
Technology CMOS EPROM, UV-erasable CMOS EPROM
Gehäuse 24-pin ceramic DIP (DC) 40-pin CDIP (CerDIP) with quartz window
Montageart Through-Hole Through-hole (DIP)
MSL-Level [DATA_NEEDED: MSL level] —
RoHS-Status [DATA_NEEDED: not explicitly stated in verified data] [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Device Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 450 gates
Maximum User I/O Pins — 36
Pin-to-Pin Propagation Delay (tpd) — 15 ns
Maximum Counter Frequency — 66.6 MHz
Supply Voltage (Vcc) — 5 V
Program/Erase Method — UV-erasable windowed CerDIP
Macrocells Configurable As — D, T, JK, SR flip-flop, or combinatorial
Development Tool — MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware — Altera Logic Programmer card
Logic Family Compatibility — Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

Datenblätter & Ressourcen

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