EP910DC-35 vs EP910DI-30 Vergleich
Detaillierter Direktvergleich von EP910DC-35 von Altera und EP910DI-30 von Rochester Electronics. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndSpezifikationsvergleich
| Parameter | EP910DC-35 | EP910DI-30 |
|---|---|---|
| Marke | Altera | Rochester Electronics |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,95 | $17,60 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | Classic EPLD (Altera EP910 series) |
| Architecture | PAL-type sum-of-products AND-OR array | — |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | — |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | 30 ns |
| Maximale Taktfrequenz | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| Betriebstemperatur | 0 °C to +70 °C (commercial) | -40C to +85C (industrial) |
| Gehäuse | 40-pin CDIP (Ceramic DIP) with quartz window | CDIP-40 (ceramic DIP, 40-pin with UV window) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | CMOS, UV-erasable EPROM |
| RoHS-Status | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Product Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Macrocell Count | — | 24 |
| Maximum Toggle Frequency (fmax) | — | 62 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Montageart | — | Through-Hole (DIP) |
| Dedicated I/O Pins | — | 12 (12 input + 12 output) |
| Output Enable Pins | — | 2 |
| Pin-Anzahl | — | 40 |
| Programmable Logic Element | — | JEDEC fuse map (3rd-party programmer) |
| Manufacturer (Original) | — | Altera (now Intel PSG) |
| Current Distributor / Authorized Aftermarket | — | Rochester Electronics, LLC |