EP910DI-35 vs EP910DC-40 Vergleich

Detaillierter Direktvergleich von EP910DI-35 von Altera und EP910DC-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DI-35 EP910DC-40
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $35,20 $13,95
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 24 24
Usable Gates 450 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 12
Bidirectional I/O Pins 20 24
Total Pins 40 —
Gehäuse CDIP-40 (Ceramic DIP with UV window) DIP-40 (ceramic, through-hole)
Montageart Through-Hole Through-Hole
Betriebstemperatur -40C to +85C (industrial) —
Technology CMOS, UV-erasable EPROM —
Programming Method EPROM programmer + JEDEC fuse map UV-erase + EPROM programmer; on-board logic test circuitry
Erasure Method UV light through quartz window —
RoHS-Status [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] [DATA_NEEDED: rohs_status]
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Device Family — Classic EPLD (EP910 series)
Architecture — PAL-type AND/OR, UV-erasable CMOS
Total Inputs to Logic Array — 36
Product Terms — 240 maximum
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Versorgungsspannung — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C

Datenblätter & Ressourcen

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