EP910DM-40 vs EP910DC-30 Vergleich
Detaillierter Direktvergleich von EP910DM-40 von Altera und EP910DC-30 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910DM-40 | EP910DC-30 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,00 | $15,60 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | Classic EPLD (EP910 series) |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | 36 |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 30 ns (max) |
| External Clocks | 2 | — |
| Process Technology | CMOS | CMOS |
| Gehäuse | 40-pin Ceramic DIP (Cerdip) with UV window | DIP-40 (through-hole, 600 mil) |
| Montageart | Through-Hole (DIP) | Through-Hole |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Versorgungsspannung | 5 V | 5 V |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Programming Method | — | UV-Erasable / OTP |