EP910DM-40 vs EP910DC-30 比較
詳細な並列比較: EP910DM-40 メーカー: Altera および EP910DC-30 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910DM-40 | EP910DC-30 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.00 | $15.60 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | Classic EPLD (EP910 series) |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND-OR sum-of-products, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | 36 |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 30 ns (max) |
| External Clocks | 2 | — |
| Process Technology | CMOS | CMOS |
| パッケージ | 40-pin Ceramic DIP (Cerdip) with UV window | DIP-40 (through-hole, 600 mil) |
| 実装タイプ | Through-Hole (DIP) | Through-Hole |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| 電源電圧 | 5 V | 5 V |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | — |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Programming Method | — | UV-Erasable / OTP |