EP910DM-40 vs EP910DC-40 Vergleich
Detaillierter Direktvergleich von EP910DM-40 von Altera und EP910DC-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910DM-40 | EP910DC-40 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,00 | $13,95 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | — |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | 12 |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | 240 maximum |
| Propagation Delay (tPD) | 40 ns | — |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| Gehäuse | 40-pin Ceramic DIP (Cerdip) with UV window | DIP-40 (ceramic, through-hole) |
| Montageart | Through-Hole (DIP) | Through-Hole |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| Versorgungsspannung | 5 V | 5 V (typical for Classic EPLD family) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |