EP910DM-40 vs EP910DC-40 Perbandingan
Perbandingan bersamaan detil EP910DM-40 dari Altera dan EP910DC-40 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910DM-40 | EP910DC-40 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | — |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | 12 |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | 240 maximum |
| Propagation Delay (tPD) | 40 ns | — |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| Paket | 40-pin Ceramic DIP (Cerdip) with UV window | DIP-40 (ceramic, through-hole) |
| Tipe Mounting | Through-Hole (DIP) | Through-Hole |
| Suhu Kerja | [DATA_NEEDED: operating temperature range] | — |
| Tegangan Pemuat | 5 V | 5 V (typical for Classic EPLD family) |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs_status] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |