EP910DM883B vs EP910DC-15 Vergleich
Detaillierter Direktvergleich von EP910DM883B von Altera und EP910DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910DM883B | EP910DC-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $10,75 |
| Manufacturer | Altera (now part of Intel) | — |
| Family | Classic EPLD - EP910 Series | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type AND-OR-NOT, CMOS | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns (typical) | — |
| Maximale Taktfrequenz | 25 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| Programming Voltage (VPP) | 12.5 V (UV-erase window) | — |
| Betriebstemperatur | -55 °C to +125 °C (military) | 0C to +70C (commercial) |
| Gehäuse | CDIP-40 (Ceramic DIP, 40-pin) | 24-pin ceramic DIP (DC) |
| Montageart | Through-Hole (DIP) | Through-Hole |
| MIL Processing | MIL-STD-883B Class B | — |
| Configuration Memory | UV-erasable EPROM | — |
| Logic Elements | Combinational + Registered | [DATA_NEEDED: exact LE count] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Density | — | 900 usable gates |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Technology | — | CMOS EPROM, UV-erasable |
| MSL-Level | — | [DATA_NEEDED: MSL level] |