EP910DM883B vs EP910DC-15 对比

详细并排对比 EP910DM883B 出自 Altera 和 EP910DC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910DM883B EP910DC-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $7.10 $10.75
Manufacturer Altera (now part of Intel) —
Family Classic EPLD - EP910 Series Altera Classic EPLD
Device Type Erasable Programmable Logic Device (EPLD) —
Architecture PAL-type AND-OR-NOT, CMOS —
Macrocells 24 24
Inputs 36 —
Outputs 24 —
Product Terms 240 —
Propagation Delay (tPD) 40 ns (typical) —
最大时钟频率 25 MHz —
Supply Voltage (VCC) 5 V 5 V (typical)
Programming Voltage (VPP) 12.5 V (UV-erase window) —
工作温度 -55 °C to +125 °C (military) 0C to +70C (commercial)
封装 CDIP-40 (Ceramic DIP, 40-pin) 24-pin ceramic DIP (DC)
安装类型 Through-Hole (DIP) Through-Hole
MIL Processing MIL-STD-883B Class B —
Configuration Memory UV-erasable EPROM —
Logic Elements Combinational + Registered [DATA_NEEDED: exact LE count]
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: not explicitly stated in verified data]
Lead-Free [DATA_NEEDED: lead-free status] —
Device Density — 900 usable gates
Dedicated Inputs — 12
Bidirectional I/O Pins — 12
Flip-Flops — 10
Product Terms per Macrocells — 24
Maximum Propagation Delay (tPD) — 15 ns
Speed Grade — 15
Technology — CMOS EPROM, UV-erasable
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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