EP910IDC-15 vs EP910IPC-12 Vergleich
Detaillierter Direktvergleich von EP910IDC-15 von Altera und EP910IPC-12 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910IDC-15 | EP910IPC-12 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $14,20 |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | Classic EPLD |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Gehäuse | 40-pin CDIP (Ceramic DIP, through-hole) | 40-pin PDIP |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 10 | 10 |
| Programming Technology | EPROM (UV-erasable) | — |
| RoHS-Status | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 450 |
| Maximum Operating Frequency (fMAX) | — | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| Montageart | — | Through Hole |
| Technology | — | CMOS EPLD (UV-erasable or OTP) |
| Betriebstemperatur | — | -40C to +85C (industrial) |
| Programming Toolchain | — | MAX+PLUS II |
| Logic Capacity | — | Equivalent to ~24 PAL16V8s |