EP910IDC-15 vs EP910IPC-12 比較
詳細な並列比較: EP910IDC-15 メーカー: Altera および EP910IPC-12 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910IDC-15 | EP910IPC-12 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $14.20 |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | Classic EPLD |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| パッケージ | 40-pin CDIP (Ceramic DIP, through-hole) | 40-pin PDIP |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 10 | 10 |
| Programming Technology | EPROM (UV-erasable) | — |
| RoHS ステータス | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 450 |
| Maximum Operating Frequency (fMAX) | — | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 12 ns |
| 実装タイプ | — | Through Hole |
| Technology | — | CMOS EPLD (UV-erasable or OTP) |
| 動作温度 | — | -40C to +85C (industrial) |
| Programming Toolchain | — | MAX+PLUS II |
| Logic Capacity | — | Equivalent to ~24 PAL16V8s |