EP910IDI-15 vs EP910DC-30 Vergleich

Detaillierter Direktvergleich von EP910IDI-15 von Altera und EP910DC-30 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910IDI-15 EP910DC-30
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $29,00 $15,60
Family Classic EPLD Classic EPLD (EP910 series)
Device Type CPLD (Complex Programmable Logic Device) —
Logic Gates 450 gates —
Macrocells 24 24
Maximum User I/O Pins 36 —
Pin-to-Pin Propagation Delay (tpd) 15 ns —
Maximum Counter Frequency 66.6 MHz —
Supply Voltage (Vcc) 5 V —
Technology CMOS EPROM —
Program/Erase Method UV-erasable windowed CerDIP —
Gehäuse 40-pin CDIP (CerDIP) with quartz window DIP-40 (through-hole, 600 mil)
Betriebstemperatur -40C to +85C (industrial, "I" grade) 0C to +70C (commercial)
Montageart Through-hole (DIP) Through-Hole
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial —
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler —
Programming Hardware Altera Logic Programmer card —
RoHS-Status [DATA_NEEDED: RoHS compliance of CDIP windowed part] —
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages —
Architecture — PAL-type AND-OR sum-of-products, CMOS
Gate Count — 900 usable gates
Propagation Delay (tPD) — 30 ns (max)
Clock Frequency (fCNT) — 33.3 MHz
Dedicated Inputs — 36
Outputs (Macrocells) — 24
External Clock Pins — 2 (CLK1, CLK2)
Versorgungsspannung — 5 V
Process Technology — CMOS
Programming Method — UV-Erasable / OTP

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