EP910IDI-15 vs EP910DC-30 比較
詳細な並列比較: EP910IDI-15 メーカー: Altera および EP910DC-30 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910IDI-15 | EP910DC-30 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $29.00 | $15.60 |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | — |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | — |
| Maximum Counter Frequency | 66.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM | — |
| Program/Erase Method | UV-erasable windowed CerDIP | — |
| パッケージ | 40-pin CDIP (CerDIP) with quartz window | DIP-40 (through-hole, 600 mil) |
| 動作温度 | -40C to +85C (industrial, "I" grade) | 0C to +70C (commercial) |
| 実装タイプ | Through-hole (DIP) | Through-Hole |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | — |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | — |
| Programming Hardware | Altera Logic Programmer card | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | — |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Dedicated Inputs | — | 36 |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| 電源電圧 | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |