EP910IPC-50 vs EP910ILC-50 Vergleich
Detaillierter Direktvergleich von EP910IPC-50 von Altera und EP910ILC-50 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910IPC-50 | EP910ILC-50 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $13,85 | $10,85 |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | — |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | 24 |
| Gehäuse | 40-pin Ceramic DIP (IPC, windowed) | PLCC-44 (J-lead) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| Betriebstemperatur | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Technology | CMOS EPROM cell | CMOS EPROM, UV-erasable |
| Programming Method | Off-board EPROM programmer + UV erase | — |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| Montageart | Through-Hole (DIP) | Surface Mount (socket-compatible) |
| RoHS-Status | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | — | 24 |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Dedicated Input Pins | — | 12 |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |