EP910IPC-50 vs EP910ILC-50 Comparaison
Comparaison détaillée côte à côte de EP910IPC-50 par Altera et EP910ILC-50 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910IPC-50 | EP910ILC-50 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $13,85 | $10,85 |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | — |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | 24 |
| Boîtier | 40-pin Ceramic DIP (IPC, windowed) | PLCC-44 (J-lead) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| Température de fonctionnement | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Technology | CMOS EPROM cell | CMOS EPROM, UV-erasable |
| Programming Method | Off-board EPROM programmer + UV erase | — |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| Type de montage | Through-Hole (DIP) | Surface Mount (socket-compatible) |
| Statut RoHS | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | — | 24 |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Dedicated Input Pins | — | 12 |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |