EP910JM-40 vs EP910DM-40 Vergleich
Detaillierter Direktvergleich von EP910JM-40 von Altera und EP910DM-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910JM-40 | EP910DM-40 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $21,00 |
| Device Family | Altera Classic EPLD | — |
| Series | EP910 | — |
| Logic Type | EPLD (UV-Erasable PAL-type) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Product Terms | 240 | 240 |
| External Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Process Technology | CMOS | CMOS |
| Gehäuse | JLCC-28 (windowed ceramic, J-lead) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Montageart | Surface Mount | Through-Hole (DIP) |
| RoHS-Status | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] | [DATA_NEEDED: RoHS compliance status] |
| Programming Method | UV erase + EPROM programmer | — |
| Betriebstemperatur | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] | [DATA_NEEDED: operating temperature range] |
| Product Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EP910 |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| External Clocks | — | 2 |
| Versorgungsspannung | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |