EP910LC-30 vs EP910LC-35H Vergleich

Detaillierter Direktvergleich von EP910LC-30 von Altera und EP910LC-35H von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910LC-30 EP910LC-35H
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $22,50 $25,00
Device Type EPLD (Erasable Programmable Logic Device) —
Macrocell Count 24 —
Propagation Delay (tPD) 30 ns (max) —
Maximum Toggle Frequency 62 MHz —
Supply Voltage (VCC) 5 V (nominal, TTL) 5 V (4.75 V to 5.25 V)
Process Technology CMOS (EPROM-based) —
Package Type PDIP-40 (Plastic DIP, through-hole) —
Operating Temperature Grade Commercial (0C to +70C) —
I/O Pin Count 24 —
Dedicated Input Pins 36 (including I/O) —
Product Terms per Macrocell Up to 16 —
Programming Technology UV-erasable EPROM cell —
Development Tool Altera MAX+PLUS II —
MSL-Level [DATA_NEEDED: MSL level] —
RoHS-Status [DATA_NEEDED: RoHS status] unknown
Family — Classic EPLD (EP910)
Logic Elements — 24 macrocells
Equivalent Gates — 450 usable gates
Propagation Delay (tpd) — 35 ns
Technology — CMOS, UV-erasable EPROM
Gehäuse — 40-pin Ceramic DIP (H suffix)
User I/O Pins — 36
Dedicated Inputs — 10
Betriebstemperatur — [DATA_NEEDED: operating temperature range grade]
Erasure Method — UV (quartz window on H package)
Programming Method — Altera hardware programmer
Logic Levels — TTL compatible
Ruhestrom — [DATA_NEEDED: typical ICC value]
Process Node — [DATA_NEEDED: process geometry]
Montageart — Through-hole (Ceramic DIP)
Lifecycle — Obsolete (long-term supply via Rochester Electronics)

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